MP1758A - Anritsu Pattern Generators

Anritsu MP1758A Overview

The MP1758A has a 4 channel data output and a 2 channel clock output. It can generate two patterns: programmable and pseudo-random. The programmable pattern can be up to 128 K bit long for each channel. In addition, seven pseudo-random patterns with periods from 27 -1 to 231 -1 can be generated with a 1/4 phase difference for each channel. The amplitude and offset voltage of the data/clock output can be set independently for each channel. The setting ranges are 0.5 to 2.0 Vp-p for amplitude, -2.0 to +2.0 VOH for offset voltage, and -500 to +500 ps for delay between the data and clock outputs. Features: Four independently adjustable output channels PRBS pattern with max. 2 31 -1 bits Built in synthesized clock signal The MP1758A has a 4 channel data output and a 2 channel clock output. It can generate two patterns: programmable and pseudo-random. The programmable pattern can be up to 128 K bit long for each channel. In addition, seven pseudo-random patterns with periods from 27 -1 to 231 -1 can be generated with a 1/4 phase difference for each channel. The amplitude and offset voltage of the data/clock output can be set independently for each channel. The setting ranges are 0.5 to 2.0 Vp-p for amplitude, -2.0 to +2.0 VOH for offset voltage, and -500 to +500 ps for delay between the data and clock outputs. Features Four independently adjustable output channels PRBS pattern with max. 2 31 -1 bits Built in synthesized clock signal The MP1758A has a 4 channel data output and a 2 channel clock output. It can generate two patterns: programmable and pseudo-random. The programmable pattern can be up to 128 K bit long for each channel. In addition, seven pseudo-random patterns with periods from 27 -1 to 231 -1 can be generated with a 1/4 phase difference for each channel. The amplitude and offset voltage of the data/clock output can be set independently for each channel. The setting ranges are 0.5 to 2.0 Vp-p for amplitude, -2.0 to +2.0 VOH for offset voltage, and -500 to +500 ps for delay between the data and clock outputs. Features Four independently adjustable output channels PRBS pattern with max. 2 31 -1 bits Built in synthesized clock signal