CTT-102 - Calculex Bit Error Rate Testers

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Technical Specifications

Max. Data Rate

Max. Clock Rate
20Mbps max

Pattern Depth
Long (32, 768 bits) or short (128 bits)

Extra Specifications
Dual Bit Error-Rate Tester

Product Description

The CTT-102 Dual Bit Error-Rate Tester (DualBERTTM ) provides basic functional end-to-end testing of two PCM links or processing devices simultaneously. The CTT-102 was designed for use in production testing or anywhere that basic functional testing is sufficient and complex link analysis is not required. By eliminating the complex circuitry required for noise generation and in-depth statistical analysis, the CTT-102 provides an economical means for thorough link testing and exercising with an optimal signal. The CTT-102 incorporates circuitry equivalent to two independent CTE-301 BERTs into one compact, portable case. The DualBERT can be used to test two circuits or devices simultaneously, and can be easily carried to field installations. The CTT-102 incorporates two independent bit pattern generators, two independent bit pattern checkers and appropriate level-translation circuitry to interface to TTL or RS-422 circuits. Front-panel adjustments allow the operator to adjust the TTL-level input thresholds, so that the instrument may accommodate test signals which are slightly distorted or attenuated. The bit-pattern generator provides continuous pseudo-random bit patterns which repeat at intervals of 127 or 32,767 bits (front-panel selectable). The bit-pattern generators will also generate 1-of-16 or alternating bit patterns. The data rate is front-panel selectable at rates from 100 bits per second to 20 megabits per second. An external clock input allows the user to test at other bit rates by injecting the appropriate clock frequency. Features: Two independent BERTs in a single portable case Generates fixed and pseudo-random bit patterns TTL and RS-422 signal levels Front-panel selectable bit rates from 100bps to 20Mbps Large, easy-to-read LED error count display Clock present, data present and sync indicators Force error function External clock inputs