1186 - DRS Technologies Bit Error Rate Testers

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Technical Specifications

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Extra Specifications
Bit Error Rate Tester

Product Description

The Model 1186 Bit Error Rate (BER) tester provides complete bit error rate testing for parallel, differential ECL data systems and cables. The unit can be rack mounted or used as a desktop system. The unit can be controlled via front panel, RS-232 or 10BaseT Ethernet. The 1186 can be fitted with various rear panel “Transition Modules”. These modules allow transition to ELCO, SDN, Amplimite, DB series and others. The user may mix and match modules for cables / systems with different connectors. Once system test is started, individual pseudorandom patterns are sent down each bit, independent verifiers synchronize on the return bits and begin to count errors. A test timer is also reset with the start of System Test, this value is displayed and allows the user to quickly correlate test time with how many errors have occurred. A more traditional Bit Error Rate that updates once per minute is also reported. The rate is based on the total number of errors divided by the total number of clock cycles since the test was started. With five errors and a clock cycle count of 109, the system would report a BER of 5x10-9. An external clock may be applied during System test, or an internal rate between 1MHZ and 110MHz may be selected.