BRL Test, Inc.

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SPG - SyntheSys Research Pattern Generators


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  • Model: SPG
  • Manufactured by: SyntheSys Research
  • Max. Data Rate: 12.50Gbps
  • Channels: n/a
  • Max. PRBS Pattern: 31
  • Pattern Depth: to 8 Mbits
  • Extra Specifications: Stressed Pattern Generator

SyntheSys Research introduces the latest member of the BERTScope family. The BERTScope SPG is a BERTScope pattern generator with the ability to add stress impairments to an internal or external clock. This makes it a cost-effective solution for testing in applications where non-BER measurements are used to calibrate the DUT, and BER is measured by the DUT itself or a legacy BERT. It is also ideal for production testing where stress is to be set up for multiple test stations.

Cost-effective stress generation for receiver jitter tolerance compliance testing for standards such as:

  • Serial ATA
  • PCI Express
  • FB-DIMM
  • SAS
  • 10GbE
  • Fibre Channel 2x, 4x, 10x
  • XFP/XFI

The instrument provides calibrated amounts of common stress impairments. For ISI insertion there is the BERTScope Differential ISI Board to provide a known, well behaved frequency response impairment unhindered by suck outs and other response issues associated with low quality switching.

External sinusoidal interference (SI) output is designed to drive a JDSU OPTX10 reference optical transmitter for 10GbE receiver stress testing. 

  • Data generator from 0.1 to 12.5 Gb/s covering all popular high speed standards
  • Calibrated insertion of the following stress types:
    • Sinusoidal Jitter (SJ)
    • Sinusoidal Interference (SI)
    • Bounded Uncorrelated (PRBS) Jitter (BUJ)
    • Random Jitter (RJ)
  • Flexible sub-rate clock outputs with large selection of divider choices for driving devices under test
  • Stressing of an external clock, including one with Spread Spectrum Clocking (SSC) for serial bus testing
  • Full rate jittered clock output for driving additional legacy pattern generators for extra test flexibility
  • Flexible pattern generation with intuitive RAM pattern editing and a library of common standards patterns such as Fibre Channel, and Serial-ATA
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